1. Field of the Invention
The invention relates to semiconductor measurements and more particularly to a method and a device for the measurement of a semiconductor memory device having a bidirectional data strobe terminal for a data strobe signal and having at least one data terminal for a data signal at a test apparatus.
2. Background of the Invention
Semiconductor memory devices are tested at test apparatuses which generally have a plurality of identical test heads which each have a plurality of test locations for semiconductor memory devices that are to be tested (also referred to herein as “devices under test”). Each test location has, inter alia, outputs (hereinafter “drivers”), and also bidirectional inputs and outputs (hereinafter “I/O ports”) for outputting and for receiving data signals.
The number of I/O ports per test location is limited and, in test apparatuses for conventional semiconductor memory devices, is based on the number of data terminals of the semiconductor memory devices. Therefore, it is generally a multiple of eight or twelve. Given maximum occupancy of a test head, all of the I/O ports of a test head are regularly used.
In the course of the test, the data signals output by the test apparatus via I/O ports transfer data to the device under test, while the data signals output via data terminals of the device under test transfer data to the test apparatus. In this case, the transfer and the evaluation of the data signals received by the test apparatus are always produced in a manner synchronized with an internal clock of the test apparatus.
Semiconductor memory devices of a newer type may also have newer architecture that comprises, in addition to the bidirectional data terminals, at least one further bidirectional terminal for a data strobe signal (data strobe terminal) operated in parallel with the data signals. The data strobe signal is output (hereinafter also: “driven”) by the semiconductor memory device during the read-out of data from the semiconductor memory device and by a memory control device (hereinafter “memory controller”) during the writing of data to the semiconductor memory device. Such a signal may serve for controlling or synchronizing write and read operations (also termed “data transfer” hereinafter).
During the testing of such semiconductor memory devices of a newer type which have a bidirectional data strobe terminal serving for synchronizing or controlling the data transfer, using a conventional test apparatus, that is, one designed for testing conventional semiconductor memory devices, problems arise with regard to the number of available I/O ports per test location and the testing of time conditions (hereinafter “timing”) of the data strobe signal.
During the read-out of data from the device under test, the test apparatus instigates the read operation and evaluates the data signals present at the I/O ports in a manner synchronized to the read operation using an internal clock of the test apparatus itself. However, if the device under test has a data strobe signal of the above-mentioned type, the evaluation of the data signals, in the case of complete testing or testing close to the application, has to be performed in a manner synchronized with the data strobe signal, which, in general, does not depend on the clock signal of the test apparatus. However, test apparatuses designed for conventional semiconductor memory devices are not designed to measure devices where the clock signal is synchronized to the device strobe signal.
The second problem relates to the resources of the test apparatus. The maximum number of possible test locations (and thus also devices under test) per test head generally results directly from the total number of I/O ports on a test head and the number of bidirectional terminals on a device under test. In the case of semiconductor memory devices of a conventional type, only data terminals are regularly bidirectional, and are generally provided in a multiple of eight or twelve in accordance with the customary data bus width. Accordingly, the total number of I/O ports is also a multiple of eight or twelve. Furthermore, the I/O ports are organized electrically, mechanically and in terms of programming, into units compatible with the data bus width and are limited in terms of their assignability to the test locations.
An additional bidirectional terminal on the semiconductor memory device reduces the number of devices under test which can be tested in a given test pass at the test apparatus, since the additionally required I/O port for the data strobe signal can only be made available by a second test location. Since the second test location is then not only blocked for accommodating a further device under test but, moreover, due to the organization of the test apparatus, is also unsuitable for making available I/O ports for other devices under test on the common test head, the number of devices under test per test pass is ultimately reduced by half.
In will therefore be appreciated that a need exists to improve test methods for newer types semiconductor memory devices.